Traditionally, the electrical connection between IC chips and the outside is achieved by bonding the I/O on the chip to the package carrier through the package pins using metal wires. With the reduction of IC chip feature size and the expansion of integration scale, the spacing of I/O is constantly decreasing and the number is constantly increasing. When the I/O spacing is reduced to below 70 um, the wire bonding technology is no longer applicable, and new technical approaches must be sought. Wafer-level packaging technology uses thin film redistribution technology to allow I/O to be distributed on the entire surface of the IC chip instead of being limited to the narrow peripheral area of the IC chip, thereby solving the electrical connection problem of high-density, fine-pitch I/O chips.

Among the many new packaging technologies, wafer-level packaging technology is the most innovative and the most eye-catching, and it is a sign of a revolutionary breakthrough in packaging technology. Wafer-level packaging technology uses wafers as processing objects, and simultaneously packages, ages, and tests many chips on the wafer, and finally cuts them into single devices. It reduces the package size to the size of the IC chip, and the production cost is greatly reduced. The advantages of wafer-level packaging technology have attracted great attention as soon as it appeared, and it has rapidly gained huge development and wide application. In portable products such as mobile phones, wafer-level packaging EPROM, IPD (integrated passive devices), analog chips and other devices have been widely used. The types of devices using wafer-level packaging are increasing, and wafer-level packaging technology is a new technology that is developing rapidly.

In order to improve the applicability of wafer-level packaging and expand its application range, people are researching and developing various new technologies while solving problems arising in the industrialization process, and conducting research on the status quo, application and development of wafer-level packaging technology.

WLP was initially developed by the manufacture of low-speed I/O and low-speed transistor components for mobile phones, such as passive on-chip sensors and power transmission ICs. Currently, WLP is in the development stage, driven by applications such as Bluetooth, GPS (Global Positioning System) components and sound cards, and demand is gradually increasing. When it comes to the production stage of 3G mobile phones, it is expected that a variety of new mobile content applications will become another growth driver for WLP, including TV tuners, FM transmitters and stacked memory. As memory device manufacturers begin to gradually implement WLP, it will lead the paradigm shift of the entire industry.

Currently, wafer-level packaging technology has been widely used in flash memory, EEPROM, high-speed DRAM, SRAM, LCD drivers, RF devices, logic devices, power/battery management devices and analog devices (regulators, temperature sensors, controllers, operational amplifiers, power amplifiers) and other fields. Wafer-level packaging mainly uses two basic technologies: thin film redistribution technology and bump formation. The former is used to convert the welding area distributed along the periphery of the chip into a bump welding area distributed in a planar array on the chip surface. The latter is used to make bumps on the bump welding area to form a solder ball array.

Film redistribution WL-CSP is the most common process used today. Because of its low cost, it is very suitable for the reliability standards of high-volume, portable product board-level applications. Like other WLPs, the wafers of thin film redistribution WL-CSP are still made using conventional wafer processes. Before the wafers are sent to the WLP supplier, they must be tested to classify the circuits and draw wafer maps of qualified circuits. Before the wafers are redistributed, the layout of the device must be evaluated to confirm whether the wafer is suitable for solder ball redistribution.

A typical redistribution process, the final solder bumps are arranged in a surface array. In this process, BCB is used as the redistribution dielectric layer, Cu is used as the redistribution wiring metal, the bump bottom metal layer (UBM) is deposited by sputtering, and the solder paste is deposited by screen printing and reflowed. The bottom metal layer process is very critical to reduce intermetallic chemical reactions and improve interconnect reliability.

The redistribution process is to rearrange the I/O pads on the surface of the device. In this example, two dielectric layers are used on the device surface, with a redistribution metallization layer in between to change the I/O distribution. After this process, solder ball bumps are electroplated and the chip becomes a WLP product.

The disadvantage of redistributing the wire bond pad design into a solder ball array pad is that the WLP product produced may not be the best in device design, structure or manufacturing cost. However, once it is proven to be technically feasible, the circuit can be redesigned so that the additional redistribution can be eliminated. This situation has become a consensus. For this purpose, a two-phase decision procedure has been defined. The next generation of changes may be the integration of the redistribution layer in the last metal layer of the chip, or a new design of the shortest signal line to improve performance.

The redesign may require the addition of new software tools. Since the redesign eliminates the additional redistribution process and related processes, the structure of the redesigned signal, power and ground lines is very cheap. Polymers are used for silicon wafer flattening, provide necessary protection for the chip, and are used as standard surface coatings. For thin-film redistribution WLP, the single-layer polymer WLP approach is a more cost-effective design.

Since its birth 50 years ago, wire bonding has been considered a universal and reliable interconnection technology. However, with the rapid development of mobile communications, Internet e-commerce wireless access systems, Bluetooth systems and GPS technology, mobile phones have become the strongest and fastest growing driving force for high-density storage. They are replacing PCs as the technology driver for high-density storage. The demand for lower cost, smaller form factor, higher-speed device performance, longer battery life, better heat dissipation, "green" processes and higher device reliability has led designers to turn their attention to flip-chip bump interconnection technology to replace traditional wire bonding technology.

The key technical driving force for the development of lead-tin bump technology comes from the continuous device size reduction. Under the 130nm technology standard, about 30% of logic chips require bump technology. However, under the 90nm technology standard, this figure jumped to 60%. When it developed to mass production of 65nm devices, the demand for gold bump technology climbed to more than 80%.

WLP is based on BGA technology and is an improved and enhanced CSP. Some people also call WLP wafer-level chip size packaging (WLP-CSP). It not only fully reflects the technical advantages of BGA and CSP, but also is a symbol of a revolutionary breakthrough in packaging technology. Wafer-level packaging technology uses batch production process manufacturing technology to reduce the package size to the size of IC chips, greatly reducing production costs, and integrating packaging with chip manufacturing, which will completely change the situation of separation between chip manufacturing and chip packaging industries. Because wafer-level packaging technology is so important, it has received great attention since its appearance and has rapidly gained huge development and wide application.

In the flip chip interconnection method, the UBM layer is the key interface layer between the metal pad and the gold bump or solder bump on the IC. This layer is one of the key factors in flip chip packaging technology and provides high reliability electrical and mechanical connections for both the circuit and solder bump of the chip. The UBM layer between the bump and the I/O pad needs to have good enough adhesion with the metal pad and the wafer passivation layer; protect the metal pad in subsequent process steps; maintain low contact resistance between the metal pad and the bump; can serve as an effective diffusion barrier between the metal pad and the bump; and can serve as a seed layer for the deposition of solder bumps or gold bumps.

The UBM layer is usually achieved by depositing multiple layers of metal on the entire wafer surface. The techniques used to deposit the UBM layer include evaporation, chemical plating, and sputtering deposition. In advanced packaging, wafer bumping is very critical from both cost and technical perspectives. In wafer bumping, metal deposition accounts for more than 50% of the total cost. The most common metal deposition steps in wafer bumping are the deposition of the under-bump metallization (UBM) and the deposition of the bump itself, which are generally achieved through electroplating.

Electroplating technology can achieve very narrow bump pitches and maintain high yields. And this technology has a wide range of applications, and can produce bumps of different sizes, pitches and geometries. Electroplating technology has been increasingly widely used in wafer bumping and has become the most practical solution.

First, the UBM layer is made on the wafer. Then a thick glue is deposited and exposed to form a template for electroplated solder. After electroplating, the photoresist is removed and the exposed UBM layer is etched away. The last process is reflow to form solder balls. The detailed process steps for electroplating micro-bumps are as follows:

(1) Evaporate/sputter the metal layer of the seed conductive layer on the wafer;

(2) Spin-coat a layer of photoresist on the wafer;

(3) Photolithography of the electrode window array pattern;

(4) Electroplating metal micro-embedded bodies through the small holes in the photoresist;

(5) Remove the photoresist;

(6) Etch the exposed seed conductive layer.

(7) Coat a thick layer of photoresist on the metal embedding body;

(8) Overlay Au bumps;

(9) Etch away part of the thick photoresist to reveal the protruding part of the metal embedding body;

(10) Electroplating Au bumps;

(11) Deposit a very thin layer of Au or Cu on top of the embedding body.

Coplanarity refers to the consistency of the height of all bumps in the wafer, which has strict requirements in the flip chip bonding process. In flip chip bonding, bump height variations can lead to uneven force distribution, chip cracking, and electrical opens. A typical requirement for bump coplanarity is that the bump height difference across the chip cannot be greater than 5μm.

Wafer-level process technologies, such as micro-pitch wafer bumps, lead pad redistribution, and integrated passive components, provide convenient solutions for many applications. At present, many IC and MEMS devices have applied these technologies. With these technologies, device packaging and testing can be achieved at the wafer level, and then the subsequent cutting process can be carried out. Usually, advanced packaging technology involves 5-100 μm thick film processes, such as thick glue spin coating, uniform exposure of thick glue with large surface fluctuations, and obtaining very steep thick glue sidewalls. The equal-magnification full-field exposure system is an equipment solution that can meet this demand. It has high output and low self-alignment cost, making it the most competitive system for projection steppers in the field of thick film lithography.

Wafer-level packaging processes include metallization, lithography, dielectric deposition and thick film photoresist spin coating, solder deposition and reflow soldering. The patterning process usually involves using several layers of metal to make the under-bump metallization layer (UBM) for the bump base. The conductivity of the bump and wafer connection must be very good, and the passivation layer and the under-bump metallization layer need to have good adhesion. The standard process flow of photoresist patterning includes cleaning, coating, pre-baking, exposure, post-baking, developing and hardening. Each process step requires a set of parameters to be defined, which have an impact on subsequent processes. After the photoresist patterning is completed, solder or gold is filled into the cavity by electroplating or evaporation. The next step is to remove the photoresist and perform a reflow process in the oven to convert the columnar bumps into spherical bumps.

The thick photoresist coating will remain on the chip as a mask for making metal solder joint micro-molds. The redistribution coating can be modified into a bump layout or as a connection for peripheral pads and area distribution pad arrays, which are made of 5-100 μm thick polysilicon films with different electrical, chemical, mechanical and thermal properties. Isolating the redistribution area traces requires materials with high strength, high thermal stability and low insulation coefficient. These materials have been developed, one class of materials is called polyimide (such as the PI series developed by DuPont), and another insulating material is cyclotene (BCB) from Dow Chemicals. PI and BCB are widely used in flip chip bump packaging and other packaging processes.

Micro-feature molds for pads, bumps and under-ball metallization structures using thick film photoresists can meet different needs in WLP. Although the commonly used metallization materials are tin-lead, gold and copper, several other materials can also be used to achieve this. Materials for standardized applications require high-resolution graphic transfer and easy stripping properties. Many practical applications require photoresist thicknesses exceeding 100μm. In order to achieve such thicknesses, manufacturers have developed suitable coating materials.

To meet these needs, manufacturers have developed corresponding materials and process equipment. Many materials can achieve "thin" photoresist coatings (i.e. 2-10 μm) on standard semiconductor process equipment. AZP4330 (Anzhi Electronic Materials Group) and Shipleys 955 (Rohm & Haas / Shipley) photoresists are used to achieve photoresist film thicknesses of 5 to 100 μm. A 25 μm thick photoresist coating can be achieved using a multilayer coating process, but this will increase production time and cost. AZ P4620 and SPR 220 single layers can achieve 25 μm thickness. For thicker coatings, the range of material and thickness selection becomes smaller. When the required photoresist coating is obtained by single layer deposition, there are many cost benefits. Therefore, it is necessary to develop photoresist materials with a single layer thickness of 50 μm and above. For example, materials such as JSR THB-611P and AZPLP100XT from Anzhi Electronic Materials Group can achieve a single layer of photoresist coating with a thickness of 60 μm and above. Recent research work is mainly to achieve a single layer of 65 μm thick photoresist coating using AZ9260 and a single layer of 100 μm thick photoresist using AZ50XT.

Thick film processes have some special requirements for the system. The alignment system must be able to uniformly identify the geometric pattern used as the alignment mark over the entire range of resist thickness and at a specific height of the wafer surface undulation. Since the exposure source uses parallel light exposure without relying on focus, it can be achieved using a proximity lithography machine combined with the shadow exposure principle. The requirements of the lithography process for the proximity mask alignment exposure machine include: high intensity, high uniformity, UV wavelength matching the sensitive wavelength of the photoresist, sub-micron alignment accuracy, and maintaining an accurate, controllable and consistent gap between the mask and the wafer during the exposure process.

EVG's NanoAlign technology is designed to highlight the advantages of full-field exposure technology with the highest alignment accuracy and resolution and the lowest cost of use. At present, all of the company's exposure machines have applied this technology. Its goals include active anomaly control and sub-100 nm dynamic alignment resolution. Its equipment includes specialized coating equipment and contact/proximity exposure machines improved from standard models. The latest 200 mm EVG6200 Infinity and 300 mm EVG IQ Aligner exposure machines have good flexibility and user-friendly interface, which can fully meet the industrial production of φ200 mm and φ300 mm wafers that require thick resist process.

Chip thinning technology is crucial in stacked chip packaging technology because it reduces the package mounting height and enables chips to be stacked without increasing the total height of the stacked chip system. Smart cards and RFID are the thinnest single-chip applications that reflect the requirements of thin wafers. Thinner chips can increase thermal cycling reliability and support thin products. However, how thin the chip is depends on the wafer diameter and WLP process. The reason is that the thin wafer surface is prone to damage, causing microcracks and wafer breakage in subsequent operations. Since the back grinding of the wafer is the final step of the wafer processing process, the degree to which the wafer can be thinned is limited by the WLP process. Therefore, wafer-level packaging is regarded as an extension of the wafer process, and the scope of application of the packaging process steps should be considered when designing the wafer process.

Poor matching of the thermal expansion coefficients of silicon and the mounting substrate is an important reason for fatigue failure of the package solder balls in thermal cycling tests and field use. In addition, this failure is also closely related to the strength of each component itself. The thinner the chip, the better the flexibility, and the fatigue resistance of the solder ball will be improved. Therefore, thinning the wafer and thus reducing the chip thickness is also one of the important measures to improve the reliability of solder bumps. Thinning the wafer before wafer-level packaging processing can easily cause the wafer to deform or even break, which is not advisable. Thinning the wafer after the wafer-level packaging process is completed is a better method, but it is difficult to implement. Wafers and thinning technologies and equipment for wafer-level packaging manufacturing are under development.

Wafer-level packaging is based on BGA technology and is an improved and enhanced CSP, which fully reflects the technical advantages of BGA and CSP. It has many unique advantages: ① High packaging processing efficiency, it is manufactured in batch production process in wafer form; ② It has the advantages of flip chip packaging, that is, light, thin, short and small; ③ The production facility cost of wafer-level packaging is low, and the manufacturing equipment of wafers can be fully utilized without investing in another packaging production line; ④ The chip design and packaging design of wafer-level packaging can be considered and carried out simultaneously, which will improve design efficiency and reduce design costs; ⑤ In the entire process of wafer-level packaging from chip manufacturing, packaging to product delivery to users, the intermediate links are greatly reduced and the cycle is shortened a lot, which will inevitably lead to cost reduction; ⑥ The cost of wafer-level packaging is closely related to the number of chips on each wafer. The more chips on the wafer, the lower the cost of wafer-level packaging. Wafer-level packaging is the smallest low-cost package. Wafer-level packaging technology is a real batch production chip packaging technology.

The advantage of WLP is that it is a chip-scale packaging (CSP) technology suitable for smaller integrated circuits. Due to the use of parallel packaging and electronic testing technology at the wafer level, the chip area can be significantly reduced while increasing production. Since parallel operations are used to connect chips at the wafer level, the cost of each I/O can be greatly reduced. In addition, the use of simplified wafer-level testing procedures will further reduce costs. Wafer-level packaging can be used to package and test chips at the wafer level.

Wafer-level packaging technology should strive to reduce costs, continuously improve reliability, and expand its application in large ICs. In terms of solder ball technology, Pb-free solder ball technology and high Pb solder ball technology will be developed. With the continuous expansion of IC wafer size and the advancement of process technology, IC manufacturers will research and develop a new generation of wafer-level packaging technology, which can not only meet the needs of φ300 mm wafers, but also adapt to the requirements of copper wiring technology and low dielectric constant interlayer dielectric technology that have emerged recently. In addition, it is also required to improve the ability of wafer-level packaging to handle current and withstand temperature. WLBI (wafer-level testing and aging) technology is also an important topic that needs to be studied. WLBI technology is to perform electrical testing and aging directly on IC wafers, which is of great significance to simplifying the process flow and reducing production costs of wafer-level packaging.

Conclusion: Wafer-level packaging technology is a low-cost mass production chip packaging technology. Wafer-level packaging is the same size as the chip and is the smallest micro surface mount device. Due to a series of advantages of wafer-level packaging, wafer-level packaging technology is booming under the impetus of the miniaturization and low-cost requirements of modern electronic devices. At present, wafer-level packaging technology is generally suitable for small-sized chips with low I/O numbers. The industry also needs to develop new technologies to reduce production costs and develop wafer-level packaging for large-sized chips and wafer-level packaging for fine-pitch solder ball arrays.

When choosing a packaging type for modern electronic devices, it is necessary to meet design requirements and minimize costs. The current level of wafer-level packaging is only one type of packaging available. There is still a lot of work to be done to make wafer-level packaging technology a mainstream manufacturing technology for large-volume and wide-ranging products in the future. Combining the design of semiconductor chips and WLP packaging will undoubtedly benefit the layout of WLP devices and improve device performance. In WLP, since the packaging steps of all devices on the wafer are carried out simultaneously, batch processing can reduce packaging costs.